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rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 1 dual output amoled bias general description the rt 4723p is a highly integrated boost , ldo and inverting charge pump to generate positive and negative output voltage. the negative output voltages can be adjusted from ? 0.6v to ? 2.4v with 100mv steps by swire interface protocol . the part maintain s the highest efficiency by utilizing a ? 0.33x/ ? 0.5x mode fractional charge pump with automatic mode transition. with its input voltage range of 2.5v to 4.6 v, the rt 4723p is optimized for products powered by single - cell battery and the output current up to 30 ma. the rt 4723p is available in wl - csp - 1 5 b 1. 3 9x 2.07 (bsc) package to achieve optimized solution for pcb space . ordering information note : richtek products are : ? rohs compliant and compatible with the current requirements of ipc/jedec j - std - 020. ? suitable for use in snpb or pb - free soldering processes . features ? 2.5v to 4.6 v supply voltage range ? single wire protocol ? fixed 4.6v positive voltage output ? negative voltage output from ? ? ? auto - mode transition of ? ? ? built - in soft - start ? 30 ma maximum output current ? programmable output fast discharge function ? high impedance output when ic s hutdown ? uvlo, o cp, s cp, otp protection ? shutdown current < 1 ? ? available in 15 - b all wl - csp package applications ? amoled bias in portable device marking information simplified application circuit p a c k a g e t y p e w s c : w l - c s p - 1 5 b 1 . 3 9 x 2 . 0 7 ( b s c ) r t 4 7 2 3 p 4 p : p r o d u c t c o d e w : d a t e c o d e 4 p w b o o s t l 1 p g n d v i n l x p s w i r e v o p v o n c 1 p r t 4 7 2 3 p g n d c i n v i n c b o o s t v o p c o p v o n c o n c 1 n c f 1 c 2 p c 2 n c f 2
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 2 pin configuration (top view) wl - csp - 15b 1.3 9 x2.07 (bsc) functional pin description pin no. pin name pin function a1 , c2, d2 gnd ground . a2 von negative terminal output. a3 c2n flying capacitor 2 negative connection. b1 swire enable and von voltage setting. b2, e1 pgnd power ground. b3 c2p flying capacitor 2 positive connection. c1 vin power input. c3 c1n flying capacitor 1 negative connection. d1 lxp switching node of boost converter. d3 c1p flying capacitor 1 positive connection. e2 b oo st output voltage of boost converter. e3 vop pos i tive terminal output. v i n p g n d c 1 n c 1 p v o p l x p v o n g n d b o o s t g n d c 2 n c 2 p s w i r e p g n d g n d c 1 c 2 c 3 d 3 d 1 e 1 e 2 e 3 d 2 a 1 a 2 a 3 b 3 b 1 b 2
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 3 functional block diagram operation the rt 4723p is a highly integrated boost , ldo and inverting charge pump to generate positive and negative output voltage. it can support input voltage range from 2.5v to 4.6v and the ou tput current up to 30ma . the vop positive output voltage is set at a typical value of 4.6v. the von negative outp ut voltage is set at a typical value of ? 2.4v and can be programmed t hrough single wire protocol (swire pin) . t he available voltage range is from ? 0.6v to ? 2.4v with 100mv per step. the rt 4723p provides over - temperature protection (otp) and short circuit protection (scp) mechanisms to prevent the device fro m damage with abnormal operations. when the swire voltage is logic low for more than 350 ? s, the ic will be shut down with low input supply current less than 1 ? a. n 1 p 1 s c p 1 r p 2 r p 1 v o p c 1 n v i n g n d p g n d l x p p w m l o g i c u v l o o c p 1 r n 2 r n 1 s c p 2 v o n d a c + - o s c i l l a t o r p u l s e c o u n t e r v r e f b a n d g a p r e f e r e n c e - 0 . 3 3 x / - 0 . 5 x c h a r g e p u m p c 1 p s o f t - s t a r t l d o + - g m v r e f d a c s w i r e v r e f f a s t d i s c h a r g e v o p v o n b o o s t c 2 p c 2 n
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 4 absol ute maximum ratings (note 1 ) ? supply input voltage v in pin -------------------------------- -------------------------------- --------------------- ? 0.3v to 6 v ? output voltage vop pin -------------------------------- -------------------------------- --------------------------- ? 0.3v to 6 v ? output voltage von pin -------------------------------- -------------------------------- --------------------------- ? 6 v to 0.3v ? others pin to gnd -------------------------------- -------------------------------- -------------------------------- -- ? 0.3v to 6 v ? power dissipation, p d @ t a = 25c wl - csp - 15b 1.3 9 x2.07 (bsc) -------------------------------- -------------------------------- ----------------- 2 w ? package thermal resistance (note 2) wl - csp - 15b 1.3 9 x2.07 (bsc) , ? j a -------------------------------- -------------------------------- ----------- 49.8 c/w ? lead temperature (soldering, 10 sec.) -------------------------------- -------------------------------- ------- 260 ? c ? junction temperature -------------------------------- -------------------------------- ----------------------------- 15 0 ? c ? storage temperature range -------------------------------- -------------------------------- -------------------- ? 65 ? c to 150 ? c ? esd susceptibility (note 3) hbm (human body model) -------------------------------- -------------------------------- ---------------------- 2 k v recommended operating conditions (note 4 ) ? supply input voltage range -------------------------------- -------------------------------- ---------------------- ? 2.5 v to 4.6 v ? positive output voltage -------------------------------- -------------------------------- ---------------------------- ? 4.6v ? negative output voltage range -------------------------------- -------------------------------- ----------------- ?? 2.4v to ? 0.6v ? ambient temperature range -------------------------------- -------------------------------- --------------------- ? ? 40 ? c to 85 ? c ? junction temperature range -------------------------------- -------------------------------- -------------------- ?? 40 ? c to 125 ? c electrical characteristics ( v in = 3. 7 v, v op = 4.6v, v on = ? 2.4v, c in = 4.7 ? f, c b oo st = 20 ? f, c o p = 10 ? f, c on = 3 0 ? f, c f1 = 1 ? f, l1 = 2.2 ? h, t a = 25c, unless otherwise specified. ) parameter symbol test conditions min typ max unit p ower supply input voltage range v in 2.5 -- 4.6 v under voltage lockout threshold voltage v uvlo_h v in rising -- 2.2 2.5 v v uvlo_hys v in hysteresis -- 100 -- mv over - temperature protection t otp (note 5) -- 140 -- ? c over - temperature protection hysteresis t otp_hyst (note 5) -- 15 -- ? c shutdown current i shdn swire = 0v -- -- 1 ? a efficiency peak 1 eff_ 1 i op = i on = 1 ma (note 5) -- 50 -- % efficiency peak 2 eff_2 i op = i on = 5 ma (note 5) -- 75 -- % efficiency peak 3 eff_3 i op = i on = 15ma (note 5) -- 84 -- % ldo output positive output voltage range v op -- 4.6 -- v positive output voltage accuracy v op_acc ? 1 -- 1 %
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 5 parameter symbol test conditions min typ max unit positive output current capability i op_max -- -- 30 ma positive output voltage ripple v op_ ripple i op = 20ma (note 5) -- 10 -- mv line regulation v op_line v in = 2. 9 to 4 .5v, i op = 2 0ma (note 5) -- 5 -- mv load regulation v op_load i op = 0ma to 30ma (note 5) -- 5 -- mv fast discharge resistance r disp -- 105 -- ? short circuit protection v scp1 -- < 80% vop -- v charge pump output negative output voltage range v on ? 2. 4 -- ? 0. 6 v negative output voltage setting range v on_set per step -- 100 -- mv negative output voltage accuracy v on_acc ? 1 -- 1 % negative output current capability i on_max (note 5) -- -- 30 ma negative charge pump switching frequency f osc_n -- 500 -- khz negative output voltage ripple v o n_ripple i on = 20ma (note 5) -- 20 -- mv line regulation v on_line v in = 2. 9 t o 4 .5v, i on = 20 ma (note 5) -- 10 -- mv load regulation v on_load i on = 0ma to 30ma (note 5) -- 30 -- mv fast discharge resistance r disn -- 60 -- ? short circuit protection v scp 2 -- > 80% v o n -- v logic input ( swire ) swire turn - off detection time t off_dly 3 50 -- -- ? s swire signal stop indicate time t stop 350 -- -- ? s twait after data t wait_int 10 -- -- ms rising input high threshold voltage level v ih 1.2 -- v in v falling input low threshold voltage level v il 0 -- 0.4 v swire pull low resistor r swire -- 300 -- k ? wake up delay t wkp -- -- 1 ? s swire rising time t r -- -- 200 n s swire falling time t f -- -- 200 n s clocked swire high t on 2 10 40 ? s clocked swire low t off 2 10 40 ? s swire to vop on time t vop_on -- 1.6 -- ms
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 6 parameter symbol test conditions min typ max unit input clocked swire frequency f swire 25 -- 250 kh z note 1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. expos ure to absolute maximum rating conditions may affect device reliability. note 2. ? ja is measured under natural convection (still air) at t a = 25 ? c with the component mounted on a high effective - thermal - conductivity four - layer test board on a jedec 51 - 7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. spec. is guaranteed by design.
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 7 typical application circuit table 1 . c omponent list of evaluation board reference qty. part number description package supplier c in 1 grm188r61c475kaaj 4.7 ? f/16v/x5r 0603 murata c boost1 , c boost2 , c op , c on1 , c on2 , c on3 6 grm188r61a106ke69 10 ? f/10v/x5r 0603 murata c f1 , c f2 2 grm155r61c105ke01 1 ? f/16v/x5r 0402 murata l1 1 glclk2r201a 2.2 ? h 2.5mm x 2.0mm x 1.0mm alps 1269as - h - 2r2m = p2 2.2 ? h murata time diagram swire interface power sequence b o o s t l 1 p g n d 4 . 7 f v i n l x p s w i r e v o p v o n c 1 p - 0 . 6 v t o - 2 . 4 v r t 4 7 2 3 p g n d e 3 a 2 d 3 b 2 , e 1 a 1 , c 2 , d 2 b 1 b 3 c 1 e 2 c i n v i n 2 . 5 v t o 4 . 6 v 2 . 2 h d 1 v o p c o p 1 0 f 4 . 6 v v o n c o n 1 1 0 f c 1 n c 3 c f 1 1 f c 2 p c 2 n a 3 c f 2 1 f 1 0 f c b o o s t 1 1 0 f c b o o s t 2 c o n 2 1 0 f c o n 3 1 0 f 9 0 % 1 0 % t o n t o f f t r t f t w k p s w i r e v o p v o n t s s 1 3 m s 0 0 0 4 . 6 v - 2 . 4 v 1 2 t s t o p > 3 5 0 s t s s 2 2 m s - 1 . 4 v t w a i t _ i n t > 1 0 m s t o f f _ d l y > 3 5 0 s 1 . 5 m s t d l y 2 . 5 m s 1 0 1 1 t v o p _ o n h i - z h i - z v i n 0
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 8 table 2 . von output voltage with swire pulse pulse von(v) 0 ? 2.4 (default) 1 ? 2.4 2 ? 2.3 3 ? 2.2 4 ? 2.1 5 ? 2.0 6 ? 1.9 7 ? 1.8 8 ? 1.7 9 ? 1.6 10 ? 1.5 11 ? 1.4 12 ? 1.3 13 ? 1.2 14 ? 1.1 15 ? 1.0 16 ? 0.9 17 ? 0.8 18 ? 0.7 19 ? 0.6 20 0 table 3 . vop/von shutdown discharge selection with swire pulse pulse discharge 21 enable once pulse 21 received on swire pin, the rt 4723p will enable the discharge function to discharge the vop/von outputs for 20ms and then enter high impedance state when fault or power - off condition. the discharge function is default disabled and outputs keep high impedance state when fault or power - off condition .
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 9 typical operating characteristics efficiency vs. output current 40 45 50 55 60 65 70 75 80 85 90 0 0.005 0.01 0.015 0.02 0.025 0.03 output current (a) efficiency (%) v in = 4.5v v in = 3.7v v in = 2.5v v op = 4.6, v on = ? 2.4v vop vs. output current 4.580 4.585 4.590 4.595 4.600 4.605 4.610 4.615 4.620 0 0.005 0.01 0.015 0.02 0.025 0.03 output current (a) vop (v) v op = 4.6, v on = ? 2.4v v in = 2.7v v in = 3.7v v in = 4.5v von vs. output current -2.410 -2.405 -2.400 -2.395 -2.390 -2.385 -2.380 -2.375 -2.370 -2.365 -2.360 0 0.005 0.01 0.015 0.02 0.025 0.03 output current (a) von (v) v op = 4.6, v on = ? 2.4v v in = 4.5v v in = 3.7v v in = 2.7v vop vs. input voltage 4.590 4.591 4.592 4.593 4.594 4.595 4.596 4.597 4.598 4.599 4.600 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) vop (v) i op = 0ma i op = 10ma i op = 30ma v op = 4.6, v on = ? 2.4v von vs. input voltage -2.41 -2.40 -2.39 -2.38 -2.37 -2.36 -2.35 2.5 3 3.5 4 4.5 input voltage (v) von (v) v op = 4.6, v on = ? 2.4v i op = 10ma i op = 0ma i op = 30ma v in = 3.7v, v op = 4.6v , v on = ? 2.4v power on time (1ms/ div ) swire ( 4 v/ div ) von (0.5v/ div ) vop (1v/ div ) i vin (0.1a/ div )
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 10 power off with discharge time ( 5ms/ div ) swire (4v/ div ) von (0.5v/ div ) vop (1v/ div ) i vin (0.1a/ div ) v in = 3.7v, v op = 4.6v , v on = ? 2.4v power off without discharge time (10ms/ div ) swire (4v/ div ) von (0.5v/ div ) vop (1v/ div ) i vin (0.1a/ div ) v in = 3.7v, v op = 4.6v , v on = ? 2.4v power on with swire is low time (10ms/ div ) swire (4v/ div ) vin ( 2 v/ div ) v boost (2v/ div ) v in = 3.7v , v op = 0v , v on = 0v v in = 3.7v, v op = 4.6v , v on = - 2.4v power on with swire is high time (10ms/ div ) swire (4v/ div ) vin (2v/ div ) v boost (2v/ div ) v in = 3.7v power on with swire from low to high time (10ms/ div ) swire (4v/ div ) vin (2v/ div ) v boost (2v/ div )
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 11 application informatio n the rt 4723p is a highly integrated boost, ldo and inverting charge pump to generate positive and negative output voltages for amloed bias. it can support input voltage range from 2. 5 v to 4.6 v and the output current up to 30 ma. the v op positive output voltage is generated from the ldo supplied from a synchronous boost converter, and v op is set at a typical value of 4.6 v. the boost converter output also drives an inverting charge pump controller to gener ate v on negative output voltage which is set at a typical value of ? 2.4 v. the negative output voltage can be programmed through the dedicated pin which implements single wire protocol and t he available voltage range is from ? 0.6 v to ? 2.4v with 100mv per st ep . input capacitor selection input ceramic capacitor with 4.7 ? f capacitance is suggested for applications. for better voltage filtering, select ceramic capacitors with low esr, x5r and x7r types are suitable because of their wider voltage and temperature ranges. boost inductor selection the inductance depends on the maximum input current. as a general rule, the inductor ripple current range is 20% to 40% of the maximum input current. if 40% is selected as an example, the inductor ripple current can be calculated according to the following equations : w here is the efficiency of the v op b oost converter, i in(max) is the maximum input current, and ? i l is the inductor ripple current. the input peak current can then be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : i peak = 1.2 x i in (max) note that the saturated current of the inductor must be greater than i peak . the inductance can eventually be determined according to the following equation : where f osc is the switching frequency. for better system performance, a shielded inductor is preferred to avoid emi problems . boost output capacitor selection the output ripple voltage is an important index for estimating ic performance. this portion consists of two parts. one is the product of ripple current with the esr of the output capacitor, while the other part is formed by the charging and discharging pro cess of the output capacitor. as shown in figure 1, ? v out1 can be evaluated based on the ideal energy equalization. according to the definition of q, the ? v out1 value can be calculated as the following equation : w here f osc is th e switching frequency and d is the duty cycle. finally, taking esr into consideration, the overall output ripple voltage can be determined by the following equation : w here ? v esr = i crms x r cesr the output capacitor, c out , should be selected accordingly. out out(max) in(max) in l in(max) vi i = v i = 0.4 i ? ? ? ?? ? ? ? ? ? ? 2 2 in out in out out(max) osc v v v l 0.4 v i f ? ? ? ? ? ? ? out out out1 soc out out1 soc out 1 q = i d = c v f id v = fc ? ? ? ? ? ? ? out out esr out1 esr osc out id v = v + v = v + fc ? ? ? ? ? ?
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 12 figure 1. output ripple voltage without contribution of esr under voltage lockout to prevent abnormal operation of the ic in low voltage condition, an under voltage lockout is included which shuts down ic operation when input voltage is lower than the specified threshold voltage. soft - start the rt 4723p employs an internal soft - start feature to avoid high inrush current during start - up. the soft - start function is achieved by clamping the output voltage o f the internal error amplifier with another voltage source that is increased slowly from zero to near vin during the soft - start period. negative output voltage setting the negative output voltage can be programmed by a mcu through the dedicated pin according to table 2 v on output voltage with swire pulse . shutdown delay and discharge when the s w ire signal is logic low for more than 350 ? s, the ic function will be shut down . t h e output v op /v on can be actively discharged to gnd with discharge function enabled referring to table 3 vop/von shutdown discharge selection with swire pulse . in shutdown mode, the input supply current for the ic is less than 1 ? a. over current protection the rt 4723p includes a cycle - by - cycle current lim it function which monitors the inductor current during each on period. the power switch will be forced off to avoid large current damage once the current is over the limit level. short circuit protection the rt 4723p has an advanced output short - circuit protection mechanism which prevents the ic from damage by unexpected applications. when the output becomes shorted to ground, and the output voltage is under the limit level with 1ms (typ.) duration, the bias function enters shutdown mode and can only re - s tart normal operation after triggering the swire pin. over temperature protection the rt 4723p equips an over temperature protection circuitry to prevent overheating due to excessive power dissipation. the otp will shut down the bias operation when ambient temperature exceeds 140 ? c . once the ambient temperature cools down by approximately 15 ? c , ic will automatically resume normal operation. to maintain continuous operation, the maximum junction temperature should be prevented from rising above 125 ? c . thermal considerations the junction temperature should never exceed the absolute maximum junction temperature t j(max) , listed under absolute maximum ratings, to avoid permanent damage to the device. the maximum allowable power dissipation depends on the thermal resistance of the ic package, the pcb layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. the maximum power dissipation can be calculated using the following formula : p d(max) = (t j(max) ? t a ) / ? ja wh ere t j(max) is the maximum junction temperature, t a is the ambient temperature, and ? ja is the junction - to - ambient thermal resistance. for continuous operation, the maximum operating junction temperature indicated under recommended operating conditions is 125 ? c. the junction - to - i n p u t c u r r e n t i n d u c t o r c u r r e n t o u t p u t c u r r e n t t i m e t i m e o u t p u t r i p p l e ( a c ) d t s ? i l ? v o u t 1
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 13 ambient thermal resistance, ? ja , is highly package dependent. for a wl - csp - 15b 1.3 9 x2.07 (bsc) package, the thermal resistance, ? ja , is 49.8 ? c/w on a standard jedec 51 - 7 high effective - thermal - conductivity four - layer test board. th e maximum power dissipation at t a = 25 ? c can be calculated as below : p d(max) = (125 ? c ? 25 ? c) / (49.8 ? c/w) = 2w for a wl - csp - 15b 1.3 9 x2.07 (bsc) package. the maximum power dissipation depends on the operating ambient temperature for the fixed t j(max) and the thermal resistance, ? ja . the derating curves in figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 2 . derating curve of maximum power dissipation layout considerations for the best performance of the rt 4723 p , the following pcb layout guidelines should be strictly followed. ? for good regulation, place the power components as close to the ic as possible. the traces should be wide and short especially for the high current ou tput loop. ? the input and output bypass capacitor should be placed as close to the ic as possible and connected to the ground plane of the pcb. ? the flying capacitor should be placed as close to the c 1p /c 1n/c2p/c2n pi n as possible to avoid noise injection. ? m inimize the size of the lx p node and keep the traces wide and short. care should be taken to avoid running traces that carry any n oise - sensitive signals near lx p or high - current traces. ? separate power ground (pgnd) and analog ground (gnd). connect the gnd and the pgnd islands at a single end. make sure that there are no other connections between these separate ground planes. 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 14 figure 3. pcb layout guide g n d c 2 n v o n s w i r e c 2 p p g n d v i n c 1 n g n d l x p c 1 p g n d p g n d v o p b o o s t l 1 c o n 1 c f 1 c f 2 s w i r e v i n v o p c b s t 1 g n d g n d c o n 2 p g n d g n d g n d c i n v o n c o n 3 c b s t 2 c o p g n d
rt4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. ds4723p - 00 december 2016 www.richtek.com 15 outline dimension symbol dimensions in millimeters dimensions in inches min. max. min. max. a 0.500 0.600 0.020 0.024 a1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 d 2.020 2.120 0.080 0.083 d1 1.600 0.063 e 1.340 1.440 0.053 0.057 e1 0.800 0.031 e 0.400 0.016 wl - csp - 15b 1.39x2.07 (bsc)
rt 4723p copyright ? 2016 richtek technology corporation. all rights reserved . is a registered trademark of richtek technology corporation. www.richtek.com ds4723p - 00 december 2016 16 footprint information package number of pin type footprint dimension (mm) tolerance e a b wl - csp1.39*2.07 - 15(bsc) 15 nsmd 0.400 0.240 0.340 0.025 smd 0.270 0.240 richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is curre nt and complete. richtek cannot assume responsibility for use of any ci rcuitry other than circuitry entirely embodied in a richtek product. information furnished by richtek is believed to be accur ate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringements of pa tents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of richtek or its su bsidiaries.

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